Programmable Logic Devices (PLDS) are Integrated Circuits (ICs) that are user configurable and capable of implementing digital logic operations. There are several types of PLDs, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). CPLDs typically include several function blocks that are based on the well-known programmable logic array (PLA) architecture, and include a central interconnect matrix to transmit signals between the function blocks. Signals are transmitted into and out of the interconnect matrix through input/output blocks (IOBs). The input/output function of the IOBs, the logic performed by the function blocks and the signal paths implemented by the interconnect matrix are all controlled by configuration data stored in configuration memory of the CPLD. FPGAs include configurable logic blocks (CLBs) arranged in rows and columns, IOBs surrounding the CLBs, and programmable interconnect lines that extend between the rows and columns of CLBS. Each CLB includes look-up tables and other configurable circuitry that is programmable to implement a portion of a larger logic function. The CLBs, IOBs and interconnect lines are configured by data stored in a configuration memory of the FPGA.
PLDs have become popular for implementing various logic functions in electronic systems that, in the recent past, were typically implemented by smaller (&lt;100,000 gates) application specific integrated circuits (ASICs). Such functions include glue logic, state machines, data bus logic, digital signal processors and protocol functions. Early PLDs often provided insufficient capacity to implement these functions, so the significant investment of time and money to design, layout and fabricate an ASIC for these functions was justified. However, recent advances in semiconductor and PLD technologies have produced PLDs with the necessary speed and capacity to implement these functions in most applications. Because PLDs are relatively inexpensive and can be programmed in as little as a few hours, the expense associated with the design, layout and fabrication of ASICs became harder to justify. Further, the reprogrammability of many PLDs makes them even more attractive than ASICs because it is possible to update (reconfigure) PLDS, whereas ASICs must be replaced. As such, there is a trend toward the use of PLDs in place of ASICS in electronic systems.
Most electronic systems include multiple ICs (such as PLDS, ASICs, memory devices and processors) mounted on a printed circuit board (PCB). Each PCB includes a pattern of printed metal lines (e.g., copper tracks) formed on a board of insulating material. The ICs are typically soldered to the copper tracks at specific locations on the PCB so that the copper tracks provide signal paths between the ICs that are necessary to form the desired electronic system.
After ICs are soldered to a PCB to form an electronic system, the system is typically tested to verify that all of the ICs are properly mounted (e.g., that the copper tracks provide all required IC-to-IC connections). Early electronic systems were tested using mechanical probes (e.g., bed-of-nails fixtures) that contacted the copper tracks of the PcBs and generated test signals for verifying the interconnections between the ICs. However, steady advances in semiconductor technologies have provided highly integrated ICs mounted in packages that have hundreds of pins arranged at very small pitches. Further, trends toward smaller products have forced manufacturers to pack ICs more densely on PCBs. As a result, conventional PCB testing methods using mechanical probes (e.g., bed-of-nails fixtures) are greatly impeded for several reasons. First, to support these highly integrated ICs, modern PCBs must be formed with copper tracks having ever-narrower widths, thereby making conventional testing difficult because test nails having very small physical dimensions are required. Second, the increase in the number of pins requires an increase in the number of copper tracks per PCB, thereby requiring test equipment that is increasingly more expensive to purchase and operate. Third, the dense packing of ICs on each PCB leaves little room for probe contact. Moreover, recent PCB technologies in which surface mounted IC devices are mounted on both sides of each PCB make mechanical probing practically impossible because of the required simultaneous probe contact on both sides of a PCB.
IEEE Standard 1149.1 (Boundary-Scan) was developed to overcome the limitations of conventional mechanical PCB probe testing. IEEE Standard 1149.1 defines a four pin serial interface that drives a 16-state controller (state machine) formed in each compliant IC device. The four pins control transitions of the state machine and facilitate loading of instructions and data into the compliant IC device to accomplish pre-defined tasks. Originally, IEEE Standard 1149.1 was developed to perform a Boundary-Scan Test wherein the interconnections and IC device placement on PCBs are tested through the connection pins of the PCBs (i.e., without the need for a mechanical probe). Since its establishment, the Boundary-Scan Test has been extended to include device functional tests, self-tests and diagnostic capabilities. More recently, the Boundary-Scan Test has been modified to provide In-System Programming, whereby configuration data is transmitted into the configuration memory of a target PLD after the PLD is mounted onto a PCB.
FIG. 1 shows a simplified electronic system provided for the purpose of explaining the basic concepts of Boundary-Scan Test procedures. The simplified electronic system is formed on a PCB 100 and includes a first PLD 110 and a second PLD 120.
PCB 100 includes copper traces formed on a board of insulating material that provide signal paths between a PCB connector 101 and PLDs 110 and 120, and between PLDs 110 and 120. In addition to the copper traces that transmit normal operation signals (not shown), PCB 100 includes four traces for transmitting Boundary-Scan Test signals. These copper traces include a first trace 102 for transmitting test data-in (TDI) signals, a second trace 103 for transmitting test data-out (TDO) signals, a third trace 104 for transmitting test clock (TCK) signals, and a fourth trace 105 for transmitting test mode select (TMS) signals. Boundary-Scan data (TDI/TDO) signals are typically transmitted serially through each compliant device of a system. That is, TDI signals are transmitted on first trace 102 to first PLD 110, and pass through first PLD 110 along a line 144(1). TDO signals are transmitted from PLD 110 and received as TDI signals by second PLD 120 along a linking trace 106, and pass through second PLD 120 along a line 144(2). Finally, TDO signals are transmitted from PLD 120 to PCB connector 101 on second trace 103. In contrast to the data signals, each compliant device receives the TCK and TMS signals in a parallel manner.
Each PLD of an electronic system includes IOBs that configure the device terminals (pins) for transmitting signals to or from the PLD's programmable core logic circuitry. As shown in FIG. 1, first PLD 110 includes I/O terminals 112 that transmit/receive signals via lines 114 through respective IOBs 116 to/from programmable core logic circuit 118. Similarly, second PLD 120 includes I/O terminals 122 that transmit/receive signals via lines 124 through IOBs 126 to/from core logic circuit 128.
Unlike ASICs, the functions performed by both core logic circuit 118 and IOBs 116 of PLD 110 are determined by a user after fabrication. That is, the user determines the function or functions to be performed by the programmable interconnect and logic circuitry associated with a PLD. Similarly, the user determines which of the I/O pins will be used for input operations, and which of the I/O pins will be used for output operations. As described in additional detail below, this requires each IOB 116 to include programmable circuitry capable of performing both input and output operations.
In addition to core logic and input/output circuitry, each IC device that complies with IEEE Standard 1149.1 includes dedicated pins and hardware elements (referred to herein as Boundary-Scan architecture) for implementing Boundary-Scan Test procedures. Referring to FIG. 1, first PLD 110 includes four pins 142(1) through 142(4) that are respectively connected to trace 102 (TDI), trace 105 (TMS), trace 104 (TCK) and trace 106 (TDO). Similarly, second PLD 120 includes four pins 142(5) through 142(8) that are respectively connected to trace 106 (TDI), trace 104 (TCK), trace 105 (TMS) and trace 103 (TDO). The data and test control circuitry of the Boundary-Scan architecture provided on each compliant device utilize the signals received on the four dedicated pins. Briefly described, the data circuitry of the Boundary-Scan architecture includes a series of Boundary-Scan Register (BSR) cells associated with the IOBs 116 and 126, and Test Control circuitry. The Test Control circuitry (which is described in additional detail below) is controlled by signals transmitted on the TDI/TDO line, the TCK and TMS signals to direct data signal shifting through the BSR cells to facilitate Boundary-Scan Testing of first PLD 110 and second PLD 120.
FIG. 2 is a detailed block diagram showing an example of the basic hardware elements provided on an IEEE Standard 1149.1 compliant PLD. The basic hardware elements include a test access port (TAP) 210, a TAP controller 220, an instruction register (IR) 230, an instruction decode circuit 235, a test data register circuit 240, an output multiplexer (MUX) 250, an output flip-flop 260 and a tri-state buffer 270.
TAP 210 provides access to the test support functions build into an IEEE Standard 1149.1 compliant PLD. TAP 210 includes three input connections for receiving the test clock input (TCK) signal, the test mode select (TMS) signal, and the test data input (TDI) signal. The TCK signal allows the Boundary-Scan architecture to operate synchronously and independently of the built-in system clock provided on the PLD. The TMS signal is used to control the state of TAP controller 220, as discussed below. The TDI signal is used for serial transmission of data or instruction bits, depending upon the state of TAP controller 220. TAP 210 may also include an optional fourth input terminal for receiving a test reset input signal for asynchronous resetting of TAP controller 220. In addition to the above-mentioned input connections, TAP 210 includes an output connection through which the TDO signals are transmitted. Depending upon the state of TAP controller 220, the TDO signal is used to serially shift either instruction register or data register contents out of the PLD.
FIG. 3 is a state diagram for explaining the operation of TAP controller 220 (shown in FIG. 2). The basic function of TAP controller 220 is to generate clock and control signals required for the correct sequence of operations of instruction register 230, test data register circuit 240, output MUX 250, output flip-flop 260 and tri-state buffer 270. Specifically, TAP controller 220 control signals that facilitate loading of instructions into instruction register 230, shifting TDI data into and TDO data out of the data registers in test data register circuit 240, and performing test actions such as capture, shift and update test data. These signals are provided in accordance with the state of TAP controller 220. All state transitions (indicated as arrows in FIG. 3) within TAP controller 220 occur in accordance with the serially received TMS values (shown next to each arrow).
TAP controller 220 is initialized to a Test-Logic Reset state 301 at power up. In this state all test logic is disabled (i.e., all core logic of the PLD operates normally). TAP controller 220 will enter Test-Logic Reset state 301 from any other state when TMS is held high (logic 1) for at least five TCK pulses.
From Test-Logic Reset state 301, TAP controller 220 enters a Run-Test/Idle state 302 when TMS is held low (logic 0) for at least one TCK pulse. TAP controller 220 is placed in this state while, for example, self-test or data scan operations are performed, and remains in this state until TMS is held high.
During test procedures, TAP controller 220 either enters a `-DR` branch of the state machine (i.e., states 303 through 309), or a `-IR` branch of the state machine (i.e., states 310 through 316). From Run-Test/Idle state 302 TAP controller 220 enters the `-DR` branch when TMS is held high (logic 1) for one TCK pulse, then held low (logic zero), thereby respectively shifting to a Select DR-Scan state 303, and then to a Capture-DR state 304. Alternately, from Run-Test/Idle state 302 TAP controller 220 enters the `-IR` branch when TMS is high (logic 1) for two TCK pulses, then low (logic zero), thereby respectively shifting through Select DR-Scan state 303 to Select IR-Scan state 310, and then to a Capture-IR state 311.
When TAP controller 220 enters the `-DR` branch of the state diagram, a selected data register (or serially connected set of registers) of test data register circuit 240 is connected between TDI and TDO (see FIG. 2). Capture-DR state 304 is used to load data from, for example, an input pin of the PLD. From Capture-DR state 304, TAP controller 220 enters an Exit1-DR state 306 when TMS is held high, or enters a Shift-DR state 305 when TMS is held low. Shift-DR state 305 is used to shift previously captured data toward the TDO connector such that the data is shifted by one serially connected register per TCK pulse. TAP controller 220 remains in Shift-DR state 305 as long as TMS remains low, and enters Exit1-DR state 306 when TMS is subsequently held high. From Exit1-DR state 306, TAP controller 220 enters either a Pause-DR state 307 when TMS is held low, or enters an Update-DR state 309 when TMS is held high. Pause-DR state 307 is provided to temporarily halt a shifting process to allow, for example, synchronization between TCK and system clock signals, when needed. TAP controller 220 remains in Pause-DR state 307 until TMS is held high, at which time it enters Exit2-DR state 308. From Exit2-DR state 308, TAP controller 220 either returns to Shift-DR state 305 when TMS is held low, or enters Update-DR state 309 when TMS is held high. Once TAP controller 220 is in Update-DR state 309, data shifting to/between the selected register(s) is completed, and the data stored in the selected register(s) is passed, for example, to the output pins of the PLD. From Update-DR state 309, TAP controller 220 either returns to Run-Test/Idle state 302 when TMS is held low, or to Select-DR state 303 when TMS is held high.
In contrast to the `-DR` branch, instruction register 230 is connected between TDI and TDO when TAP controller 220 enters the `-IR` branch (states 310 through 316) of the state diagram. The `-IR` branch is used to load instructions that are used, for example, to select a data register (or serially-connected set of registers) of test data register circuit 240 for subsequent test data operations. As can be observed in FIG. 3, states 310 through 316 of the `-IR` branch are respectively similar to states 303 through 309 of the `-DR` branch, and provide similar functions with respect to instruction register 230. Therefore, these states will not be discussed in further detail.
Referring again to FIG. 2, instruction register 230 receives and stores test instructions transmitted to the PLD. When TAP controller 220 is in Shift-IR state 312 (see FIG. 3), a series of instruction registers are connected in series between the TDI and TDO connectors. The test instruction data subsequently shifted into the instruction registers defines the test data register to be addressed and the test to be performed.
FIG. 4 is a schematic diagram showing an instruction register cell 400 for storing one instruction bit in the instruction register. Instruction register cell 400 includes a multiplexer (MUX) 410, a shift register flip-flop 420 and a parallel latch 430. The selected data is transmitted to shift register MUX 410 transmits either design specific DATA (optional) or instruction data shifted from a previous cell of the instruction register in accordance with a SHIFT-IR control signal generated by the TAP controller. Shift register flip-flop 420 stores the received data in response to a CLOCK IR control signal generated by the TAP controller, and transmits the stored data to a next cell in the instruction register (or to TDO if transmitted from the last cell) and to parallel latch 430. Parallel latch 430 either stores the data from shift register flip-flop 420, or resets in response to a RESET signal. After instruction data is shifted into all of the shift register flip-flop 420, the instruction data is parallel loaded into the parallel latches 430 of each cell in response to an UPDATE-IR signal from the TAP controller. Instruction data stored in each parallel latch 430 is transmitted with information from the other cells of instruction register 230 to instruction decode circuit 235 (see FIG. 2), which generates appropriate control signals that are used to control test data register circuit 240.
Referring again to FIG. 2, test data register circuit 240 receives the TDI input signal, and includes several data registers (or groups of registers) that are connected in parallel. These data registers include two required registers (i.e., a bypass register 242 and at least one BSR cell 243) and one or more optional data registers 244. Optional registers 244 may include, for example, a device ID register 245, a user-assigned ID register 246 and an ISP configuration register 247. An output multiplexer (MUX) 248 that connects a selected one of the data registers to TDO during data shifting operations.
Bypass register 242 is a single stage shift register that provides a minimum length serial path for the test data shifting through the PLD to, for example, another IC on the PCB (both not shown) of an electronic system including the PLD.
FIG. 5 is a schematic diagram showing a conventional BSR cell 243 for storing one data bit used during Boundary-Scan Test procedures. Multiple BSR cells 243 are linked in the manner described below to form a Boundary-Scan Register (BSR) whereby test data bits are shifted along the BSR to implement Boundary-Scan Test procedures. Each BSR cell 243 includes an input multiplexer (MUX) 510, a shift register flip-flop 520, a parallel latch 530 and an output MUX 540. Input MUX 510 is controlled by a SHIFT/LOAD-DR control signal to either load SYSTEM DATA or shift TDI data from a previous cell of the BSR. The selected data is transmitted to shift register flip-flop 520 that stores the received data in response to a CLOCK DR control signal generated by the TAP controller. Shift register flip-flop 520 transmits the stored data either to a next of the BSR cell (or to TDO if transmitted from the last cell) and to parallel latch 530. Parallel latch 530 stores the data from shift register flip-flop 520 in response to an UPDATE-DR control signal from the TAP controller, and transmits this data to output MUX 540. Output MUX 540 is controlled by a MODE TEST/NORM control signal from the instruction register to either transmit SYSTEM data (during normal operation) or the contents of parallel latch 540 (during Boundary-Scan Test procedures). The signal from output MUX 540 is either transmitted to the core logic (when BSR cell 243 is associated with an input pin) or to the output pin of the PLD.
Referring again to FIG. 2, optional device ID register 244 and user-assigned ID register 245 provide binary information regarding the manufacturer, part number, version number and any user-assigned information used to identify the PLD within a system. These registers are important for verifying correct installation/replacement of the PLD, and are used, for example, to identify the PLD during ISP.
Finally, optional ISP configuration register 246 allow serial shifting of ISP data using the TDI/TDO line, and parallel shifting of this data into the configuration memory of the PLD. Each ISP configuration register 246 is constructed similar to instruction register cell 400 (see FIG. 4).
The data signals output from instruction register 230 and test data register circuit 240 are transmitted to output MUX 250, which is controlled by a SELECT SIGNAL generated by TAP controller 220. In this way TAP controller 220 controls the transmission of instruction data or test data on the TDI/TDO line. The selected data is transmitted through output flip-flop 260 and tri-state buffer 270 to the TDO connector in TAP 210.
FIG. 6 is a simplified schematic diagram showing an IOB 116 that includes a portion of a BSR formed along line 144(1) of first PLD 110 (see FIG. 1). IOB 116 includes an input buffer IB, a tri-state buffer TS and BSR cells 243 (1) through 243 (3). IOB 116 is configured by an output enable (OE) signal (which is transmitted through BSR cell 243(3)) either to receive input data signals applied to an I/O pin 112, or to transmit output data signals to I/O pin 112. When the OE signal is in a first state (e.g., low), IOB 116 is configured for receiving input signals from I/O pin 112 (i.e., tri-state buffer TS is set in a tri-state mode). In the input mode, input buffer IB transmits DATA IN signals applied to I/O pin 112 through BSR cell 243(1) and on a SYSTEM INPUT line to, for example, the PLD core logic circuit. Conversely, when the OE signal is in a second state (e.g., high), IOB 116 is configured for transmitting output signals to I/O pin 112. In the output mode, output signals transmitted on a SYSTEM OUTPUT line from, for example, the PLD core logic circuit are applied to I/O pin 112 through BSR cell 243(2) and tri-state buffer TS.
BSR cells 243(1) through 243(3) each include the data register architecture discussed above with respect to FIG. 5. During Boundary-Scan Test procedures, Boundary-Scan Test data signals are serially transmitted through BSR cells 243(1) through 243(3) in response to the SHIFT-DR and CLOCK-DR signals generated by the TAP controller. Specifically, BSR cell 243(1) receives a TDI signal from a previous BSR cell (not shown) of the BSR on line segment 144(A). This TDI signal is shifted through multiplexer 510(1) and shift register flip-flop 520(1) and transmitted to BSR cell 243(2). Subsequently, BSR cell 243(2) shifts this TDI signal through multiplexer 510(2) and shift register flip-flop 520(2), and transmits it to BSR cell 243(3). Finally, BSR cell 243(3) shifts the TDI signal through multiplexer 510(3) and shift register flip-flop 520(3), and transmits it on line segment 144(B) to a subsequent IOB associated with the BSR.
FIG. 7 is a simplified schematic diagram showing a conventional IEEE Standard 1149.1 compliant PLD 700 in which portions of programmable core logic circuit 718 are utilized to implement two distinct logic equations. PLD 700 includes nine IOBs 116-1 through 116-9, each including three BSR cells (243-X1 through 243-X3) that are serially connected to form a BSR along line 744. The serial connections between the BSR cells of the BSR are fixed (i.e., not alterable) in the manner shown in FIG. 6. Note that the BSR is 27 BSR cells in length (nine IOBs multiplied by three BSR cells per IOB).
A problem associated with conventional IEEE Standard 1149.1 compliant ICs arises because the length (i.e., number of BSR cells) and configuration (i.e., the serial connection of the BSR cells) of the BSR is fixed by the fixed serial connection between the BSR cells. For example, referring to FIG. 7, test data must be transmitted to all 27 BSR cells of the BSR associated with PLD 700 even if test data is only needed in a small number of the BSR cells. For example, if a particular Boundary-Scan Test procedure calls for test data only in BSR cells 243-91, 243-92 and 243-93 of IOB 116-9, the procedure must also include "dummy" test data values for each of the BSR cells of IOBs 116-1 through 116-8 in order to shift the test data into the target BSR cells of IOB 116-9. This fixed BSR architecture requires that the function (i.e., input or output) of all device pins must be determined before Boundary-Scan Test procedures can be generated for a conventional IEEE Standard 1149.1 compliant PLD.
In some situations involving the use of conventional IEEE Standard 1149.1 compliant ICs, particularly those involving PLDs, the device pin functions are not known until they are established by a user. For example, again referring to FIG. 7, PLD 700 is configured by a user to implement two discrete logic functions using core logic portions 718(A) and 718(B). In this example, IOBs 116-1 and 116-9 are configured to pass input signals to portion 718(A), and IOB 116-8 is configured to pass the resulting output signal to its associated device pin. Similarly, IOBs 116-2, 116-4, 116-6 and 116-9 are configured to pass input signals to portion 718(B), and IOB 116-5 is configured to pass the resulting output signal to its associated device pin. Until these pin assignments are established by the user, the pin functions associated with pins of PLD 700 are not known. To further complicate matters, some PLDs allow reconfiguration of logic and IOBs during execution of a logic operation, thereby further complicating the process of identifying the device pin functions.
In addition, some of the device pins may not be used in a particular implementation. For example, again referring to FIG. 7, the device pin associated with IOB 116-3 is not used by either of the portions 118(A) and 118(B). However, because BSR cells 243-31, 243-32 and 243-33 are fixed in the BSR, these BSR cells must be accounted for in the Boundary-Scan Test procedure.
Moreover, data must be shifted through all BSR cells during Boundary-Scan Test procedures, even when only a few device pins are being tested. For example, assume a user wishes only to test the logic function associated with portion 718(A). In order to transmit data into the BSR cells of IOBs 116-1, 116-8 and 116-9 to perform this test, data must also be transmitted to all of the BSR cells associated with IOBs 116-3 through 116-7.
In each of the examples provided above, the problem presented by the fixed BSR is that shifting data signals through unused or non-relevant BSR cells causes delays during test procedures. When several tests are performed, these delays significantly increase the test period, thereby increasing production costs.
What is needed is a BSR cell that is programmable to facilitate removal from the BSR of an IC, thereby providing a BSR having various lengths and configurations, and thereby reducing the time required to perform Boundary-Scan Test procedures.